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? semiconductor components industries, llc, 2010 march, 2017 ? rev. 18 1 publication order number: ar0330cm/d ar0330cm 1/3\inch cmos digital image sensor description the ar0330 from on semiconductor is a 1/3-inch cmos digital image senso r with an active-pixel array of 2304 (h) 1536 (v). it can support 3.15 mp (2048 (h) 1536 (v)) digital still image capture and a 1080p60 + 20% eis (2304 (h) 1296 (v)) digital video mode. it incorporates sophisticated on-chip camera functions such as windowing, mirroring, column and row sub-sampling modes, and snapshot modes. table 1. key performance parameters parameter typical value optical format 1/3-inch (6.0 mm) entire array: 6.09 mm still image: 5.63 mm (4:3) hd image: 5.82 mm (16:9) active pixels 2304 (h) 1536 (v): (entire array) 5.07mm (h) 3.38mm (v) 2048 (h) 1536 (v) (4:3, still mode) 2304 (h) 1296 (v) (16:9, hd mode) pixel size 2.2 2.2 m color filter array rgb bayer shutter type ers and grr input clock range 6?27 mhz output clock maximum 196 mp/s (4-lane hispi or mipi) output video ? 4-lane hispi 2304 1296 at 60 fps < 450 mw (v cm 0.2 v, 198 mp/s) 2304 1296 at 30 fps < 300 mw (v cm 0.2 v, 98 mp/s) responsivity 2.0 v/lux ? sec snr max 39 db dynamic range 69.5 db supply voltage digital analog hispi phy hispi i/o (slvs) hispi i/o (hivcm) i/o/digital 1.7?1.9 v (1.8 v nominal) 2.7?2.9 v 1.7?1.9 v (1.8 v nominal) 0.3?0.9 v (0.4 or 0.8 v nominal) 1.7?1.9 v (1.8 v nominal) 1.7?1.9 v (1.8 v nominal) or 2.4?3.1 v (2.8 v nominal) operating temperature (junction) ? t j ?30 c to + 70 c package options clcc ? 11.4 mm 11.4mm csp ? 6.28 mm 6.65 mm bare die features ? 2.2 m pixel with a ? pix technology ? full hd support at 60 fps (2304 (h) 1296 (v)) for maximum video performance ? superior low-light performance ? 3.4 mp (3:2) and 3.15 mp (4:3) still images ? support for external mechanical shutter ? support for external led or xenon flash ? data interfaces: four-lane serial high-speed pixel interface (hispi) differential signaling (slvs), four-lane serial mipi interface, or parallel ? on-chip phase-locked loop (pll) oscillator ? simple two-wire serial interface ? auto black level calibration ? 12-to-10 bit output a ? law compression ? slave mode for precise frame-rate control and for synchronizing two sensors applications ? 1080p high-definition digital video camcorder ? web cameras and video conferencing cameras ? security see detailed ordering and shipping information on page 2 of this data sheet. ordering information clcc48 case 848au odcsp64 case 570bh www.onsemi.com
ar0330cm www.onsemi.com 2 ordering information table 2. available part numbers part number product description orderable product attribute description ar0330cm1c00shaa0 ? dp 3 mp 1/3 cis dry pack with protective film ar0330cm1c00shaa0 ? dr 3 mp 1/3 cis dry pack without protective film ar0330cm1c00shaa0 ? tp 3 mp 1/3 cis tape & reel with protective film ar0330cm1c00shka0 ? cp 3 mp 1/3 cis chip tray with protective film ar0330cm1c00shka0 ? cr 3 mp 1/3 cis chip tray without protective film ar0330cm1c12shaa0 ? dp 3 mp 1/3 cis dry pack with protective film ar0330cm1c12shaa0 ? dr 3 mp 1/3 cis dry pack without protective film ar0330cm1c12shka0 ? cp 3 mp 1/3 cis chip tray with protective film ar0330cm1c12shka0 ? cr 3 mp 1/3 cis chip tray without protective film ar0330cm1c21shka0 ? cp 3 mp 1/3 cis chip tray with protective film ar0330cm1c21shka0 ? cr 3 mp 1/3 cis chip tray without protective film general description the ar0330 can be operated in its default mode or programmed for frame size, exposure, gain, and other parameters. the default mode output is a 2304 1296 image at 60 frames per second (fps). the sensor outputs 10- or 12-bit raw data, using either the parallel or serial (hispi, mipi) output ports. functional overview the ar0330 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. it uses an on-chip, phase-locked loop (pll) that can generate all internal clocks from a single master input clock running between 6 and 27 mhz. the maximum output pixel rate is 196 mp/s using a 4-lane hispi or mipi serial interface and 98 mp/s using the parallel interface. figure 1. block diagram ext clock two-wire serial i/f pll timing and control registers analog core row drivers pixel array column amplifiers adc 12-bit 12-bit 12-bit digital core row noise correction black level correction digital gain data pedestal test pattern generator output data-path compression (optional) 12-bit 10- or 12-bit 8-, 10- or 12-bit parallel i/o: pixclk, fv, lv, d out [11:0] mipi i/o: clk p/n, data[11:0] p/n hispi i/o: slvs c p/n, slvs[3:0] p/n user interaction with the sensor is through the two-wire serial bus, which communicates with the array control, analog signal chain, and digital signal chain. the core of the sensor is a 3.4 mp active-pixel sensor array. the timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. in the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. the exposure is controlled by varying the time interval between reset and readout. once a row has been read, the signal from the column is amplified in a column amplifier and then digitized in an analog-to-digital converter (adc). the output from the adc is a 12-bit value for each pixel in the array. the adc output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain).
ar0330cm www.onsemi.com 3 working modes the ar0330 sensor working modes are specified from the following aspect ratios: table 3. available aspect ratios in the ar0330 sensor aspect ratio sensor array usage 3:2 still format #1 2256 (h) 1504 (v) 4:3 still format #2 2048 (h) 1536 (v) 16:10 still format #3 2256 (h) 1440 (v) 16:9 hd format 2304 (h) 1296 (v) the ar0330 supports the following working modes. to operate the sensor at full speed (196 mp/s) the sensor must use the 4-lane hispi or mipi interface. the sensor will operate at half-speed (98 mp/s) when using the parallel interface. table 4. available working modes in the ar0330 sensor mode aspect ratio active readout window sensor output resolution fps (4-lane mipi/ hispi interface) fps (parallel interface) subsampling fov 1080p + eis 16:9 2304 1296 2304 1296 60 n/a ? 100% 30 30 ? 100% 3m still 4:3 2048 1536 2048 1536 30 25 ? 100% 3:2 2256 1504 2256 1504 30 25 ? 100% wvga + eis 16:9 2304 1296 1152 648 60 60 2 2 100% wvga + eis slow-motion 16:9 2304 1296 1152 648 120 n/a 2 2 100% vga video 16:10 2256 1440 752 480 60 60 3 3 96% vga video slow-motion 16:10 2256 1440 752 480 215 107 3 3 96% hispi power supply connections the hispi interface requires two power supplies. the v dd _hispi powers the digital logic while the v dd _hispi_tx powers the output drivers. the digital logic supply is a nominal 1.8 v and ranges from 1.7 to 1.9 v. the hispi drivers can receive a supply voltage of 0.4 to 0.8 v or 1.7 to 1.9 v. the common mode voltage is derived as half of the v dd _hispi _tx supply. two settings are available for the output common mode voltage: 1. slvs mode: the v dd _hispi_tx supply must be in the range of 0.4 to 0.8 v and the high_vcm register bit r0x306e[9] must be set to ?0?. the output common mode voltage will be in the range of 0.2 to 0.4 v. 2. hivcm mode: the v dd _hispi_tx supply must be in the range of 1.7 to 1.9 v and the high_vcm register bit r0x306e[9] must be set to ?1?. the output common mode voltage will be in the range of 0.76 to 1.07 v. two prior naming conventions have also been used with the v dd _hispi and v dd _hispi_tx pins: 1. digital logic supply was named v dd _slvs while the driver supply was named v dd _slvs_tx. 2. digital logic supply was named v dd _phy while the driver supply was named v dd _slvs.
ar0330cm www.onsemi.com 4 typical configurations figure 2. serial 4-lane hispi interface 1. all power supplies must be adequately decoupled. on semiconductor recommends having 1.0 f and 0.1 f decoupling capacitors for every power supply. if space is a concern, then priority must be given in the following order: v aa , v aa _pix, v dd _pll, v dd _io, and v dd . actual values and results may vary depending on layout and design considerations. 2. to allow for space constraints, on semiconductor recommends having 0.1 f decoupling capacitor inside the module as close to the pads as possible. in addition, place a 10 f capacitor for each supply off-module but close to each supply. 3. on semiconductor recommends a resistor value of 1.5 k , but a greater value may be used for slower two-wire speed. 4. this pull-up resistor is not required if the controller drives a valid logic level on s clk at all times. 5. on semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes i s minimized. 6. test pin should be tied to d gnd . 7. set high_vcm (r0x306e[9]) to 0 (default) to use the v dd _hispi_tx in the range of 0.4?0.8 v. set high_vcm to 1 to use a range of 1.7?1.9 v. 8. the package pins or die pads used for the mipi data and clock as well as the parallel interface must be left floating. 9. the v dd _mipi package pin and sensor die pad should be connected to a 2.8 v supply as v dd _mipi is tied to the v dd _pll supply both in the package routing and also within the sensor die itself. 10. if the shutter or flash pins or pads are not used, then they must be left floating. 11. if the trigger pin or pad is not used then it should be tied to d gnd . 12. the gnd_slvs pad must be tied to d gnd . it is connected this way in the clcc and csp packages. notes: shutter slvs0_p slvs0_n slvs1_p slvs1_n slvs2_p slvs2_n v dd _pll v dd _io v aa v aa _pix a gnd d gnd v aa _pix v aa v dd _io v dd s data s clk extclk 1.5 k 3 1.5 k 3, 4 trigger oe_bar reset_bar test to controller (hispi-serial interface) from controller master clock (6 ? 27 mhz) digital i/o power 1 digital core power 1 analog power 1 analog power 1 analog ground digital ground v dd _hispi_tx hispi power 1 v dd _pll pll power 1 slvs3_p slvs3_n slvsc_p slvsc_n v dd _hispi_tx v dd v dd _hispi gnd_slvs s addr v dd _mipi v dd _hispi flash 0.1 f 1.0 f 0.1 f 1.0 f 0.1 f 1.0 f 0.1 f 1.0 f 0.1 f 1.0 f 0.1 f 1.0 f 0.1 f 1.0 f
ar0330cm www.onsemi.com 5 figure 3. serial mipi 1. all power supplies must be adequately decoupled. on semiconductor recommends having 1.0 f and 0.1 f decoupling capacitors for every power supply. if space is a concern, then priority must be given in the following order: v aa , v aa _pix, v dd _pll, v dd _mipi, v dd _io, and v dd . actual values and results may vary depending on layout and design considerations. 2. to allow for space constraints, on semiconductor recommends having 0.1 f decoupling capacitor inside the module as close to the pads as possible. in addition, place a 10 f capacitor for each supply off-module but close to each supply. 3. on semiconductor recommends a resistor value of 1.5 k , but a greater value may be used for slower two-wire speed. 4. this pull-up resistor is not required if the controller drives a valid logic level on s clk at all times. 5. on semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes i s minimized. 6. test pin must be tied to d gnd for the mipi configuration. 7. on semiconductor recommends that gnd_mipi be tied to d gnd . 8. v dd _mipi is tied to v dd _pll in both the clcc and the csp package. on semiconductor strongly recommends that v dd _mipi must be connected to a v dd _pll in a module design since v dd _pll and v dd _mipi are tied together in the die. 9. the package pins or die pads used for the hispi data and clock as well as the parallel interface must be left floating. 10. hispi power supplies (v dd _hispi and v dd _hispi_tx) can be tied to ground. 11. if the shutter or flash pins or pads are not used, then they must be left floating. 12. if the trigger pin or pad is not used then it should be tied to d gnd . notes: flash data1_p data1_n data2_p data2_n data3_p data3_n v dd _pll v dd _io v aa v aa _pix a gnd d gnd v aa _pix v aa v dd _io v dd s data s clk extclk 1.5 k 3 1.5 k 3, 4 trigger oe_bar reset_bar test to controller (mipi-serial interface) from controller master clock (6 ? 27 mhz) digital i/o power 1 digital core power 1 analog power 1 analog power 1 analog ground digital ground v dd _pll pll power 1 data4_p data4_n clk_p clk_n v dd s addr v dd _mipi shutter 0.1 f 1.0 f 0.1 f 1.0 f 0.1 f 1.0 f 0.1 f 1.0 f 0.1 f 1.0 f
ar0330cm www.onsemi.com 6 figure 4. parallel pixel data interface 1. all power supplies must be adequately decoupled. on semiconductor recommends having 1.0 f and 0.1 f decoupling capacitors for every power supply. if space is a concern, then priority must be given in the following order: v aa , v aa _pix, v dd _pll, v dd _io, and v dd . actual values and results may vary depending on layout and design considerations. 2. to allow for space constraints, on semiconductor recommends having 0.1 f decoupling capacitor inside the module as close to the pads as possible. in addition, place a 10 f capacitor for each supply off-module but close to each supply. 3. on semiconductor recommends a resistor value of 1.5 k , but a greater value may be used for slower two-wire speed. 4. this pull-up resistor is not required if the controller drives a valid logic level on s clk at all times. 5. on semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes i s minimized. 6. test pin should be tied to the ground. 7. the data and clock package pins or die pads used for the hispi and mipi interface must be left floating. 8. the v dd _mipi package pin and sensor die pad should be connected to a 2.8 v supply as it is tied to the v dd _pll supply both in the package routing and also within the sensor die itself. hispi power supplies (v dd _hispi and v dd _hispi_tx) can be tied to ground. 9. if the shutter or flash pins or pads are not used, then they must be left floating. 10. if the trigger pin or pad is not used then it should be tied to d gnd . notes: frame_valid line_valid pixclk shutter v dd _io v dd v aa v aa _pix a gnd d gnd v aa _pix v aa v dd _io v dd extclk s data s clk 1.5 k 3 1.5 k 3, 4 trigger oe_bar reset_bar test to controller from controller master clock (6 ? 27 mhz) digital i/o power 1 digital core power 1 analog power 1 analog power 1 analog ground digital ground d out [11:0] pll power 1 v dd _pll v dd _pll 0.1 f 1.0 f 0.1 f 1.0 f 0.1 f 1.0 f 0.1 f 1.0 f 0.1 f 1.0 f flash s addr
ar0330cm www.onsemi.com 7 pin descriptions table 5. pin descriptions name type description reset_bar input asynchronous reset (active low). all settings are restored to factory default. extclk input master input clock, range 6 ? 27 mhz. oe_bar input output enable (active low). only available on bare die version. trigger input receives slave mode vd signal for frame rate synchronization and trigger to start a grr frame. s addr input two-wire serial address select. s clk input two-wire serial clock input. s data i/o two-wire serial data i/o. pixclk output pixel clock out. d out is valid on rising edge of this clock. d out [11:0] output parallel pixel data output. flash output flash output. synchronization pulse for external light source. can be left floating if not used. frame_valid output asserted when d out data is valid. line_valid output asserted when d out data is valid. v dd power digital power. v dd _io power io supply power. v dd _pll power pll power supply. the mipi power supply (v dd _mipi) is tied to v dd _pll in both packages. d gnd power digital gnd. v aa power analog power. v aa _pix power pixel power. a gnd power analog gnd. test input enable manufacturing test modes. tie to d gnd for normal sensor operation. shutter output control for external mechanical shutter. can be left floating if not used. slvs0_p output hispi serial data, lane 0, differential p. slvs0_n output hispi serial data, lane 0, differential n. slvs1_p output hispi serial data, lane 1, differential p. slvs1_n output hispi serial data, lane 1, differential n. slvs2_p output hispi serial data, lane 2, differential p. slvs2_n output hispi serial data, lane 2, differential n. slvs3_p output hispi serial data, lane 3, differential p. slvs3_n output hispi serial data, lane 3, differential n. slvsc_p output hispi serial ddr clock differential p. slvsc_n output hispi serial ddr clock differential n. data1_p output mipi serial data, lane 1, differential p. data1_n output mipi serial data, lane 1, differential n. data2_p output mipi serial data, lane 2, differential p. data2_n output mipi serial data, lane 2, differential n. data3_p output mipi serial data, lane 3, differential p. data3_n output mipi serial data, lane 3, differential n. data4_p output mipi serial data, lane 4, differential p. data4_n output mipi serial data, lane 4, differential n.
ar0330cm www.onsemi.com 8 table 5. pin descriptions (continued) name description type clk_p output output mipi serial clock, differential p. clk_n output output mipi serial clock, differential n. v dd _hispi power 1.8 v power port to hispi digital logic. v dd _hispi_tx power 0.4 ? 0.8 v or 1.7 ? 1.9 v. refer to ?hispi power supply connections?. v aa _hv_npix power power supply pin used to program the sensor otpm (one-time programmable memory). this pin should be open if otpm is not used. table 6. csp (hispi/mipi) package pinout 1 2 3 4 5 6 7 8 a v aa v aa _hv_npix a gnd a gnd v aa v dd test d gnd b d gnd nc v aa _pix d gnd v dd _io trigger reset_bar extclk c v dd shutter d gnd slvsc_p slvs3_p slvs3_n slvs2_n slvs2_p d s addr s clk sdata flash slvsc_n slvs1_p v dd _hispi_tx v dd _hispi e v dd _io v dd _io clk_n clk_p d gnd slvs1_n slvs0_n slvs0_p f d gnd v dd _io d gnd d gnd data4_p data_n data_p v dd _pll g v dd _io v dd d gnd v dd _io data4_n data3_n data2_n v dd h d gnd v dd _io v dd _io d gnd v dd _pll data3_p data2_p v dd _pll note: nc = no connection. figure 5. clcc package pin descriptions data4_n data4_p data3_n data3_p clk_n clk_p data2_n data2_p data1_n data1_p v dd _pll d gnd v aa _pix a gnd v aa d gnd extclk reset_bar trigger shutter test v dd v dd _io d gnd v aa _hv_npix nc d gnd v dd d gnd s addr s clk s data flash v dd _io v dd d gnd slvs3_p slvs3_n slvs2_p slvs2_n slvsc_p slvsc_n v dd _hispi v dd _hispi_tx slvs1_p slvs1_n slvs0_p slvs0_n 48 43 1 6 42 31 30 19 7 18 note: pins labeled nc (not connected) should be tied to ground.
ar0330cm www.onsemi.com 9 sensor initialization power-up sequence the recommended power-up sequence for the ar0330cs is shown in figure 6. the available power supplies (v dd _ io, v dd _pll, v dd _mipi, v aa , v aa _ pix) must have the separation specified below. 1. turn on v dd _ pll and v dd _mipi power supplies. 2. after 100 s, turn on v aa and v aa _ pix power supply. 3. after 100 s, turn on v dd power supply. 4. after 100 s, turn on v dd _io power supply. 5. after the last power supply is stable, enable extclk. 6. assert reset_bar for at least 1 ms. 7. wait 150,000 extclk periods (for internal initialization into software standby. 8. write r0x3152 = 0xa114 to configure the internal register initialization process. 9. write r0x304a = 0x0070 to start the internal register initialization process. 10. wait 150,000 extclk periods. 11. configure pll, output, and image settings to desired values. 12. wait 1ms for the pll to lock. 13. set streaming mode (r0x301a[2] = 1). figure 6. power up extclk v aa _pix v aa (2.8) v dd _io (1.8/2.8) v dd (1.8) v dd _pll, v dd _mipi (2.8) t 0 t 1 t 2 t 3 t 4 t 5 t x hard reset internal initialization software standby pll clock streaming reset_bar t 6 internal initialization r0x3152 = 0xa114 r0x304a = 0x0070 notes: 1. a software reset (r0x301a[0] = 1) is not necessary after the procedure described above since a hard reset will automatically triggers a software reset. independently executing a software reset, should be followed by steps seven through thirteen above. 2. the sensor must be receiving the external input clock (extclk) before the reset pin is toggled. the sensor will begin an inte rnal initialization sequence when the reset pin toggle from low to high. this initialization sequence will run using the external input clock. power on default state is software standby state, need to apply two-wire serial commands to start streaming. above power up sequence is a genera l power up sequence. for different interface configurations, mipi, and parallel, some power rails are not needed. those not needed powe r rails should be ignored in the general power up sequence. table 7. power-up sequence symbol definition min typ max unit t 0 v dd _pll, v dd _mipi to v aa /v aa _pix (note 3) 0 100 ? s t 1 v aa /v aa _pix to v dd 0 100 ? s t 2 v dd to v dd _io 0 100 ? s t x external clock settling time (note 1) ? 30 ? ms t 3 hard reset (note 2) 1 ? ? ms t 4 internal initialization 150000 ? ? extclks t 5 internal initialization 150000 ? ? extclks t 6 pll lock time 1 ? ? ms 1. external clock settling time is component-dependent, usually taking about 10?100 ms. 2. hard reset time is the minimum time required after power rails are settled. in a circuit where hard reset is held down by rc circuit, then the rc time must include the all power rail settle time and xtal settle time. 3. it is critical that v dd _pll is not powered up after the other power supplies. it must be powered before or at least at the same time as the others. if the case happens that v dd _pll is powered after other supplies then sensor may have functionality issues and will experience high current draw on this supply. 4. v dd _mipi is tied to v dd _ pll in the both the clcc and csp packages and must be powered to 2.8 v. the v dd _hispi and v dd _hispi_tx supplies do not need to be turned on if the sensor is configured to use the mipi or parallel interface.
ar0330cm www.onsemi.com 10 power-down sequence the recommended power-down sequence for the ar0330 is shown in figure 7. the available power supplies (v dd _ io, v dd _hispi, v dd _ hispi _ tx, v dd _pll, v dd _mipi, v aa , v aa _pix) must have the separation specified below. 1. disable streaming if output is active by setting standby r0x301a[2] = 0. 2. the soft standby state is reached after the current row or frame, depending on configuration, has ended. 3. turn off v dd _hispi_tx. 4. turn off v dd _ io. 5. turn off v dd and v dd _ hispi. 6. turn off v aa /v aa _pix. 7. turn off v dd _pll, v dd _mipi. figure 7. power down extclk v dd _pll, v dd _mipi (2.8) v dd _io (1.8/2.8) v dd , v dd _hispi (1.8) v dd _hispi_tx (0.4) t 0 power down until next power up cycle t 1 t 2 t 3 t 4 v aa _pix, v aa (2.8) table 8. power-down sequence symbol parameter min typ max unit t 0 v dd _hispi _ tx to v dd _ io 0 ? ? s t 1 v dd _ io to v dd and v dd _ hispi 0 ? ? s t 2 v dd and v dd _ hispi to v aa /v aa _pix 0 ? ? s t 3 v aa /v aa _pix to v dd _pll 0 ? ? s t 4 pwrdn until next pwrup time 100 ? ? ms note: t 4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged.
ar0330cm www.onsemi.com 11 electrical characteristics table 9. dc electrical definitions and characteristics (mipi mode) (f extclk = 24 mhz; v dd = 1.8 v; v dd _io = 1.8 v; v aa = 2.8 v; v aa _pix = 2.8 v; v dd _pll = 2.8 v; output load = 68.5 pf; t j = 60 c; data rate = 588 mbps; 2304 1296 at 60 fps) symbol definition min typ max unit v dd core digital voltage 1.7 1.8 1.9 v v dd _io i/o digital voltage 1.7 2.4 1.8 2.8 1.9 3.1 v v aa analog voltage 2.7 2.8 2.9 v v aa _pix pixel supply voltage 2.7 2.8 2.9 v v dd _pll pll supply voltage 2.7 2.8 2.9 v v dd _mipi mipi supply voltage 2.7 2.8 2.9 v i (v dd ) digital operating current ? 114 136 ma i (v dd _io) i/o digital operating current ? 0 0 ma i (v aa ) analog operating current ? 41 53 ma i (v aa _pix) pixel supply current ? 9.9 12 ma i (v dd _pll) pll supply current ? 15 27 ma i (v dd _mipi) mipi digital operating current ? 35 49 ma table 10. dc electrical definitions and characteristics (hispi mode) (f extclk = 24 mhz; v dd = 1.8 v; v dd _io = 1.8 v; v aa = 2.8 v; v aa _pix = 2.8 v; v dd _pll = 2.8 v; v dd _hispi = 1.8 v, v dd _hispi_tx = 0.4 v; output load = 68.5 pf; t j = 60 c; data rate = 588 mbps; dll set to 0; 2304 1296 at 60 fps) symbol definition min typ max unit v dd core digital voltage 1.7 1.8 1.9 v v dd _io i/o digital voltage 1.7 2.4 1.8 2.8 1.9 3.1 v v aa analog voltage 2.7 2.8 2.9 v v aa _pix pixel supply voltage 2.7 2.8 2.9 v v dd _pll pll supply voltage 2.7 2.8 2.9 v v dd _hispi hispi digital voltage 1.7 1.8 1.9 v v dd _hispi_tx hispi i/o digital voltage 0.3 1.7 0.4 1.8 0.9 1.9 v i (v dd ) digital operating current ? 96.3 137 ma i (v dd _io) i/o digital operating current ? 0 0 ma i (v aa ) analog operating current ? 45.1 53 ma i (v aa _pix) pixel supply current ? 10.5 12 ma i (v dd _pll) pll supply current ? 6.4 11 ma i (v dd _hispi) hispi digital operating current ? 21.8 36 ma i (v dd _hispi_tx) hispi i/o digital operating current ? 22.3 40 ma
ar0330cm www.onsemi.com 12 table 11. dc electrical definitions and characteristics (parallel mode) (f extclk = 24 mhz; v dd = 1.8 v; v dd _io = 1.8 v; v aa = 2.8 v; v aa _pix = 2.8 v; v dd _pll = 2.8 v; output load = 68.5 pf; t j = 60 c; 2304 1296 at 30 fps) symbol definition min typ max unit v dd core digital voltage 1.7 1.8 1.9 v v dd _io i/o digital voltage 1.7 2.4 1.8 2.8 1.9 3.1 v v aa analog voltage 2.7 2.8 2.9 v v aa _pix pixel supply voltage 2.7 2.8 2.9 v v dd _pll pll supply voltage 2.7 2.8 2.9 v i (v dd ) digital operating current ? 66.5 75 ma i (v dd _io) i/o digital operating current ? 24 35 ma i (v aa ) analog operating current ? 36 44 ma i (v aa _pix) pixel supply current ? 10.5 18 ma i (v dd _pll) pll supply current ? 6 11 ma table 12. standby power (f extclk = 24 mhz; v dd = 1.8 v; v dd _io = 1.8 v; v aa = 2.8 v; v aa _pix = 2.8 v; v dd _pll = 2.8 v; output load = 68.5 pf; t j = 60 c) power typ max unit hard standby (clk off) digital 19.8 35.8 a analog 5.8 7.0 a soft standby (clk off) digital 23.5 39.7 a analog 5.4 5.9 a soft standby (clk on) digital 15700 16900 a analog 5.5 5.7 a caution: stresses greater than those listed in t able 13 may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. table 13. absolute maximum ratings symbol definition min max unit v dd _max core digital voltage ?0.3 2.4 v v dd _io_max i/o digital voltage ?0.3 4 v v aa _max analog voltage ?0.3 4 v v aa _pix pixel supply voltage ?0.3 4 v v dd _pll pll supply voltage ?0.3 4 v v dd _mipi mipi supply voltage ?0.3 4 v v dd _hispi_max hispi digital voltage ?0.3 2.4 v v dd _hispi_tx_max hispi i/o digital voltage ?0.3 2.4 v t st storage temperature ?40 85 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected.
ar0330cm www.onsemi.com 13 two-wire serial register interface the electrical characteristics of the two-wire serial register interface (s clk , s data ) are shown in figure 8 and table 14. figure 8. two-wire serial bus timing parameters s data s clk s sr p s t f t r t f t r t su;dat t hd;sta t su;sto t su;sta t buf t hd;dat t high t low t hd;sta note: read sequence: for an 8-bit read, read waveforms start after write command and register address are issued. table 14. two-wire serial bus characteristics (f extclk = 27 mhz; v dd = 1.8 v; v dd _io = 2.8 v; v aa = 2.8 v; v aa _pix = 2.8 v; v dd _pll = 2.8 v; t a = 25 c) parameter symbol standard mode fast mode unit min max min max s clk clock frequency t scl 0 100 0 400 khz hold time (repeated) start condition after this period, the first clock pulse is generated t hd;sta 4.0 ? 0.6 ? s low period of the s clk clock t low 4.7 ? 1.3 ? s high period of the s clk clock t high 4.0 ? 0.6 ? s set-up time for a repeated start condition t su;sta 4.7 ? 0.6 ? s data hold time t hd;dat 0 (note 4) 3.45 (note 5) 0 (note 6) 0.9 (note 5) s data set-up time t su;dat 250 ? 100 (note 6) ? ns rise time of both s data and s clk signals t r ? 1000 20 + 0.1 cb (note 7) 300 ns fall time of both s data and s clk signals t f ? 300 20 + 0.1 cb (note 7) 300 ns set-up time for stop condition t su;sto 4.0 ? 0.6 ? s bus free time between a stop and start condition t buf 4.7 ? 1.3 ? s capacitive load for each bus line cb ? 400 ? 400 pf serial interface input pin capacitance cin_si ? 3.3 ? 3.3 pf s data max load capacitance cload_sd ? 30 ? 30 pf s data pull-up resistor rsd 1.5 4.7 1.5 4.7 k 1. this table is based on i 2 c standard (v2.1 january 2000). philips semiconductor. 2. two-wire control is i 2 c-compatible. 3. all values referred to v ihmin = 0.9 v dd and v ilmax = 0.1 v dd levels. sensor exclk = 27 mhz. 4. a device must internally provide a hold time of at least 300 ns for the s data signal to bridge the undefined region of the falling edge of s clk . 5. the maximum t hd;dat has only to be met if the device does not stretch the low period (t low ) of the s clk signal. 6. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the s clk signal. if such a device does stretch the low period of the s clk signal, it must output the next data bit to the s data line t r max + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the s clk line is released. 7. cb = total capacitance of one bus line in pf.
ar0330cm www.onsemi.com 14 figure 9. i/o timing diagram extclk pixclk data[11:0] frame_valid/ line_valid pxl_0 pxl_1 pxl_2 pxl_n t pfl t pll t fp t rp t f t r 90% 90% 90% 90% 10% 10% 10% 10% t extclk t pd t plh t pfh frame_valid leads line_valid by 609 pixclks frame_valid trails line_valid by 16 pixclks t cp t pd note: pll disabled for t cp . table 15. i/o parameters (f extclk = 24 mhz; v dd = 1.8 v; v aa = 2.8 v; v aa _pix = 2.8 v; v dd _pll = 2.8 v; output load = 68.5 pf; t j = 60 c; clk_op = 98 mp/s) symbol definition condition min max unit v ih input high voltage v dd _io = 1.8 v v dd _io = 2.8 v 1.4 2.4 v dd _io + 0.3 v dd _io + 0.3 v v il input low voltage v dd _io = 1.8 v v dd _io = 2.8 v gnd ? 0.3 gnd ? 0.3 0.4 0.8 v i in input leakage current no pull-up resistor; v in = v dd or d gnd ?20 20 a v oh output high voltage at specified i oh v dd _io ? 0.4 ? v v ol output low voltage at specified i ol ? 0.4 v i oh output high current at specified v oh ? ?12 ma i ol output low current at specified v ol ? 9 ma i oz tri-state output leakage current ? 10 a table 16. i/o timing (f extclk = 24 mhz; v dd = 1.8 v; v dd _io = 1.8 v; v aa = 2.8 v; v aa _pix = 2.8 v; v dd _pll = 2.8 v; output load = 68.5 pf; t j = 60 c; clk_op = 98 mp/s) symbol definition conditions min typ max unit f extclk input clock frequency pll enabled 6 24 27 mhz t extclk input clock period pll enabled 166 41 20 ns t r input clock rise time 0.5 ? sine wave rise time ns t f input clock fall time 0.5 ? sine wave fall time ns clock duty cycle 45 50 55 % t jitter input clock jitter ? ? 0.3 ns output pin slew fastest c load =15pf ? 0.7 ? v/ns f pixclk pixclk frequency default ? 80 ? mhz t pd pixclk to data valid default ? ? 3 ns t pfh pixclk to frame_valid high default ? ? 3 ns t plh pixclk to line_valid high default ? ? 3 ns t pfl pixclk to frame_valid low default ? ? 3 ns t pll pixclk to line_valid low default ? ? 3 ns
ar0330cm www.onsemi.com 15 table 17. parallel i/o rise slew rate (f extclk = 24 mhz; v dd = 1.8 v; v aa = 2.8 v; v aa _pix = 2.8 v; v dd _pll = 2.8 v; output load = 68.5 pf; t j = 60 c; clk_op = 98 mp/s) vdd_io parallel slew rate (r0x306e[15:13]) unit 0 1 2 3 4 5 6 7 1.70 v 0.069 0.115 0.172 0.239 0.325 0.43 0.558 0.836 v/ns 1.80 v 0.078 0.131 0.195 0.276 0.375 0.507 0.667 1.018 1.95 v 0.093 0.156 0.233 0.331 0.456 0.62 0.839 1.283 2.50 v 0.15 0.252 0.377 0.539 0.759 1.07 1.531 2.666 2.80 v 0.181 0.305 0.458 0.659 0.936 1.347 1.917 3.497 3.10 v 0.212 0.361 0.543 0.78 1.114 1.618 2.349 4.14 hispi transmitter note: refer to ?high-speed serial pixel interface physical layer specification v2.00.00? for further explanation of the hispi transmitter specification. slvs electrical specifications table 18. power supply and operating temperature (f extclk = 24 mhz; v dd = 1.8 v; v dd _io = 1.8 v; v aa = 2.8 v; v aa _pix = 2.8 v; v dd _pll = 2.8 v; output load = 68.5 pf; t j = 60 c; clk_op = 98 mp/s) symbol parameter min typ max unit i dd _hispi_tx slvs current consumption (notes 1, 2) ? ? n 18 ma i dd _hispi hispi phy current consumption (notes 1, 2, 3) ? ? n 45 ma t j operating temperature (note 4) ? 30 ? 70 c 1. where ?n? is the number of phys. 2. temperature of 25 c. 3. up to 700 mbps. 4. specification values may be exceeded when outside this temperature range. table 19. slvs electrical dc specification (t j = 25 c) symbol parameter min typ max unit v cm slvs dc mean common mode voltage 0.45 * v dd _tx 0.5 * v dd _tx 0.55 * v dd _tx v |v od | slvs dc mean differential output voltage 0.36 * v dd _tx 0.5 * v dd _tx 0.64 * v dd _tx v v cm change in v cm between logic 1 and 0 ? ? 25 mv |v od | change in |v od | between logic 1 and 0 ? ? 25 mv nm v od noise margin ? ? 30 % | v cm | difference in v cm between any two channels ? ? 50 mv | v od | difference in v od between any two channels ? ? 100 mv v cm_ac common-mode ac voltage (pk) without vcm cap termination ? ? 50 mv v cm_ac common-mode ac voltage (pk) with vcm cap termination ? ? 30 mv v od_ac maximum overshoot peak |v od | ? ? 1.3 * |v od | v v diff_pk-pk maximum overshoot v diff_pk-pk ? ? 2.6 * v od v r o single-ended output impedance 35 50 70 r o output impedance mismatch ? ? 20 %
ar0330cm www.onsemi.com 16 table 20. slvs electrical timing specification symbol parameter min max unit 1/ui data rate (note 1) 280 700 mbps t pw bitrate period (note 1) 1.43 3.57 ns t pre max setup time from transmitter (notes 1, 2) 0.3 ? ui t post max hold time from transmitter (notes 1, 2) 0.3 ? ui t eye eye width (notes 1, 2) ? 0.6 ui t totaljit data total jitter (pk-pk) @1e ? 9 (notes 1, 2) ? 0.2 ui t ckjit clock period jitter (rms) (note 2) ? 50 ps t cycjit clock cycle-to-cycle jitter (rms) (note 2) ? 100 ps t r rise time (20 ? 80%) (note 3) 150 ps 0.25 ui t f fall time (20 ? 80%) (note 3) 150 ps 0.25 ui dcyc clock duty cycle (note 2) 45 55 % t chskew mean clock to data skew (notes 1, 4) ? 0.1 0.1 ui t physkew phy-to-phy skew (notes 1, 5) ? 2.1 ui t diffskew mean differential skew (note 6) ? 100 100 ps 1. one ui is defined as the normalized mean time between one edge and the following edge of the clock. 2. taken from the 0 v crossing point with the dll off. 3. also defined with a maximum loading capacitance of 10 pf on any pin. the loading capacitance may also need to be less for higher bitr ates so the rise and fall times do not exceed the maximum 0.3 ui. 4. the absolute mean skew between the clock lane and any data lane in the same phy between any edges. 5. the absolute skew between any clock in one phy and any data lane in any other phy between any edges. 6. differential skew is defined as the skew between complementary outputs. it is measured as the absolute time between the two complementary edges at mean vcm point. note that differential skew also is related to the vcm_ac spec which also must not be exceeded. hivcm electrical specifications the hispi 2.0 specification also defines an alternative signaling level mode called hivcm. both v od and v cm are still scalable with v dd _hispi_tx, but with v dd _ hispi_tx nominal set to 1.8 v the common-mode is elevated to around 0.9 v. table 21. hivcm power supply and operating temperatures symbol parameter min typ max unit i dd _hispi_tx hivcm current consumption (notes 1, 2) ? ? n * 34 ma i dd _hispi hispi phy current consumption (notes 1, 2, 3) ? ? n * 45 ma t j operating temperature (note 4) ? 30 ? 70 c 1. where ?n? is the number of phys. 2. temperature of 25 c. 3. up to 700 mbps. 4. specification values may be exceeded when outside this temperature range.
ar0330cm www.onsemi.com 17 table 22. hivcm electrical voltage and impedance specification (t j = 25 c) symbol parameter min typ max unit v cm hivcm dc mean common mode voltage 0.76 0.90 1.07 v |v od | hivcm dc mean differential output voltage 200 280 350 mv v cm change in v cm between logic 1 and 0 ? ? 25 mv |v od | change in |v od | between logic 1 and 0 ? ? 25 mv nm v od noise margin ? ? 30 % | v cm | difference in v cm between any two channels ? ? 50 mv | v od | difference in v od between any two channels ? ? 100 mv v cm_ac common-mode ac voltage (pk) without v cm cap termination ? ? 50 mv v cm_ac common-mode ac voltage (pk) with v cm cap termination ? ? 30 mv v od_ac maximum overshoot peak |v od | ? ? 1.3 * |v od | v v diff_pk-pk maximum overshoot v diff pk-pk ? ? 2.6 * v od v r o single-ended output impedance 40 70 100 r o output impedance mismatch ? ? 20 % table 23. hivcm electrical ac specification symbol parameter min max unit 1/ui data rate (note 1) 280 700 mbps t pw bitrate period (note 1) 1.43 3.57 ns t pre max setup time from transmitter (notes 1, 2) 0.3 ? ui t post max gold time from transmitter (notes 1, 2) 0.3 ? ui t eye eye width (notes 1, 2) ? 0.6 ui t totaljit data total jitter (pk-pk) @1e ? 9 (notes 1, 2) ? 0.2 ui t ckjit clock period jitter (rms) (note 2) ? 50 ps t cycjit clock cycle-to-cycle jitter (rms) (note 2) ? 100 ps t r rise time (20 ? 80%) (note 3) 150 ps 0.3 ui t f fall time (20 ? 80%) (note 3) 150 ps 0.3 ui d cyc clock duty cycle (note 2) 45 55 % t chskew clock to data skew (notes 1, 4) ? 0.1 0.1 ui t physkew phy-to-phy skew (notes 1, 5) ? 2.1 ui t diffskew mean differential skew (note 6) ? 100 100 ps 1. one ui is defined as the normalized mean time between one edge and the following edge of the clock. 2. taken from the 0 v crossing point with the dll off. 3. also defined with a maximum loading capacitance of 10 pf on any pin. the loading capacitance may also need to be less for higher bitr ates so the rise and fall times do not exceed the maximum 0.3 ui. 4. the absolute mean skew between the clock lane and any data lane in the same phy between any edges. 5. the absolute mean skew between any clock in one phy and any data lane in any other phy between any edges. 6. differential skew is defined as the skew between complementary outputs. it is measured as the absolute time between the two complementary edges at mean v cm point. note that differential skew also is related to the vcm_ac spec which also must not be exceeded.
ar0330cm www.onsemi.com 18 electrical definitions figure 10 is the diagram defining differential amplitude v od , v cm, and rise and fall times. to measure v od and v cm use the dc test circuit shown in figure 11 and set the hispi phy to constant logic 1 and logic 0. measure v oa , v ob and v cm with voltmeters for both logic 1 and logic 0. figure 10. single-ended and differential signals v oa v ob v od v od_ac v cm v oa v ob 2 80% 20% t f t r 0 v v diff v diff_pkpk v od = |v oa ? v ob | v od = |v ob ? v oa | differential signal single-ended signals figure 11. dc test circuit v oa v ob v cm v v 50 50 v od (m) v oa (m) v ob (m) (eq. 1) where m is either ?1? for logic 1 or ?0? for logic 0. v od v od (1) v od (0) 2 (eq. 2) v diff v od (1) v od (0) (eq. 3) v od v od (1) v od (0) (eq. 4) v cm v cm (1) v cm (0) 2 (eq. 5) v cm v cm (1) v cm (0) (eq. 6) both v od and v cm are measured for all output channels. the worst case v od is defined as the largest difference in v od between all channels regardless of logic level. and the worst case v cm is similarly defined as the largest difference in v cm between all channels regardless of logic level.
ar0330cm www.onsemi.com 19 timing definitions 1. timing measurements are to be taken using the square wave test mode. 2. rise and fall times are measured between 20% to 80% positions on the differential waveform, as shown in figure 10. 3. mean clock-to-data skew should be measured from the 0 v crossing point on clock to the 0 v crossing point on any data channel regardless of edge, as shown in figure 12. this time is compared with the ideal data transition point of 0.5 ui with the difference being the clock-to-data skew (see equation 7). t chskew (ps) t t pw 2 (eq. 7) t chskew (ui) t t pw 0.5 (eq. 8) figure 12. clock-to-data skew timing diagram t pw 1 ui 0.5 ui t t chskew clock data 4. the differential skew is measured on the two single-ended signals for any channel. the time is taken from a transition on v oa signal to corresponding transition on v ob signal at v cm crossing point. figure 13. differential skew t diffskew v cm v cm v cm_ac v cm_ac common-mode ac signal figure 13 also shows the corresponding ac v cm common-mode signal. differential skew between the v oa and v ob signals can cause spikes in the common-mode, which the receiver needs to be able to reject. v cm_ac is measured as the absolute peak deviation from the mean dc v cm common-mode.
ar0330cm www.onsemi.com 20 transmitter eye mask figure 14. transmitter eye mask normalized time 0 0.2 0.37 0.5 0.63 1 0.8 ? 1.3 * v od ? v od ? 0.7 * v od 0 0.7 * v od v od 1.3 * v od differential amplitude eye width eye height t pre t post figure 14 defines the eye mask for the transmitter. 0.5 ui point is the instantaneous crossing point of the clock. the area in white shows the area data is prohibited from crossing into. the eye mask also defines the minimum eye height, the data t pre and t post times, and the total jitter pk-pk +mean skew (t tjskew ) for data. clock signal t hclk is defined as the high clock period, and t lclk is defined as the low clock period as shown in figure 15. the clock duty cycle d cyc is defined as the percentage time the clock is either high (t hclk ) or low (t lclk ) compared with the clock period t. figure 15. clock duty cycle t hclk t lclk clock t 2 ui d cyc (1) t hclk t (eq. 9) d cyc (0) t lclk t (eq. 10) t pw t 2 (i.e, 1 ui) (eq. 11) bitrate 1 t pw (eq. 12)
ar0330cm www.onsemi.com 21 figure 16 shows the definition of clock jitter for both the period and the cycle-to-cycle jitter. figure 16. clock jitter t lclk t hclk t pw t ckjit (rms) period jitter (t ckjit ) is defined as the deviation of the instantaneous clock t pw from an ideal 1 ui. this should be measured for both the clock high period variation t hclk, and the clock low period variation t lclk taking the rms or 1-sigma standard deviation and quoting the worse case jitter between t hclk and t lclk . cycle-to-cycle jitter (t cycjit ) is defined as the dif ference in time between consecutive clock high and clock low periods t hclk and t lclk , quoting the rms value of the variation (t hclk ? t lclk ). if pk-pk jitter is also measured, this should be limited to 3-sigma. table 24. hivcm electrical ac specification symbol parameter min max unit 1/ui data rate (note 1) 280 700 mbps t pw bitrate period (note 1) 1.43 3.57 ns t pre max setup time from transmitter (notes 1, 2) 0.3 ? ui t post max gold time from transmitter (notes 1, 2) 0.3 ? ui t eye eye width (notes 1, 2) ? 0.6 ui t totaljit data total jitter (pk-pk) @1e ? 9 (notes 1, 2) ? 0.2 ui t ckjit clock period jitter (rms) (note 2) ? 50 ps t cycjit clock cycle-to-cycle jitter (rms) (note 2) ? 100 ps t r rise time (20 ? 80%) (note 3) 150 ps 0.3 ui t f fall time (20 ? 80%) (note 3) 150 ps 0.3 ui d cyc clock duty cycle (note 2) 45 55 % t chskew clock to data skew (notes 1, 4) ? 0.1 0.1 ui t physkew phy-to-phy skew (notes 1, 5) ? 2.1 ui t diffskew mean differential skew (note 6) ? 100 100 ps 1. one ui is defined as the normalized mean time between one edge and the following edge of the clock. 2. taken from the 0 v crossing point with the dll off. 3. also defined with a maximum loading capacitance of 10 pf on any pin. the loading capacitance may also need to be less for higher bitr ates so the rise and fall times do not exceed the maximum 0.3 ui. 4. the absolute mean skew between the clock lane and any data lane in the same phy between any edges. 5. the absolute mean skew between any clock in one phy and any data lane in any other phy between any edges. 6. differential skew is defined as the skew between complementary outputs. it is measured as the absolute time between the two complementary edges at mean v cm point. note that differential skew also is related to the vcm_ac spec which also must not be exceeded.
ar0330cm www.onsemi.com 22 sequencer the sequencer digital block determines the order and timing of operations required to sample pixel data from the array during each row period. it is controlled by an instruction set that is programmed into ram from the sensor otpm (one time programmable memory). the otpm is configured during production. the instruction set determines the length of the sequencer operation that determines the ?adc readout limitation? (equation 5) listed in the sensor frame rate section. the instruction set can be shortened through register writes in order to achieve faster frame rates. instructions for shortening the sequencer can be found in the ar0330 developer guide. the sequencer digital block can be reprogrammed using the following instructions: program a new sequencer. 1. place the sensor in standby. 2. write 0x8000 to r0x3088 (?seq_ctrl_port?). 3. write each instruction incrementally to r0x3086. each write must be 16-bit consisting of two bytes {byte[n], byte[n+1]}. 4. if the sequencer consists of an odd number of bytes, set the last byte to ?0?. read the instructions stored in the sequencer. 1. place the sensor in standby. 2. write 0xc000 to r0x3088 (?seq_ctrl_port?). 3. sequentially read one byte at a time from r0x3086 with 8-bit read command. sensor pll vco the sensor contains a phase-locked loop (pll) that is used for timing generation and control. the required vco clock frequency is attained through the use of a pre-pll clock divider followed by a multiplier (see figure 17). the multiplier is followed by set of dividers used to generate the output clocks required for the sensor array, the pixel analog and digital readout paths, and the output parallel and serial interfaces. dual readout paths there are two readout paths within the sensor digital block (see figure 18). the sensor row timing calculations refers to each data-path individually. for example, the sensor default configuration uses 1248 clocks per row (line_length_pck) to output 2304 active pixels per row. the aggregate clocks per row seen by the receiver will be 2496 clocks (1248 2 readout paths). figure 17. relationship between readout clock and peak pixel rate pre_pll_clk_div 2(1 ? 64) pll_multiplier 58(32 ? 384) f vco extclk (6 ? 27 mhz) figure 18. sensor dual readout paths pixel array all digital blocks all digital blocks clk_pix clk_pix serial output (mipi or hispi) pixel rate = 2 clk_pix = # data lanes clk_op (hispi or mipi) = clk_op (parallel)
ar0330cm www.onsemi.com 23 parallel pll configuration figure 19. pll for the parallel interface (the parallel interface has a maximum output data-rate of 98 mpixel/s) pre_pll_clk_div 2(1 ? 64) f vco extclk (6 ? 27 mhz) pll_multiplier 58(32 ? 384) vt_sys_clk_div 1(1, 2, 4, 6, 8, 10, 12, 14, 16) vt_pix_clk_div 6(4 ? 16) clk_op (max 98 mpixel/s) clk_pix (max 49 mpixel/s) 1/2 the maximum output of the parallel interface is 98 mpixel/s (clk_op). this will limit the readout clock (clk_pix) to 49 mpixel/s. the sensor will not use the f serial , f serial_clk , or clk_op when configured to use the parallel interface. table 25. pll parameters for the parallel interface symbol parameter min max unit extclk external clock 6 27 mhz f vco vco clock 384 768 mhz clk_pix readout clock 49 mpixel/s clk_op output clock 98 mpixel/s table 26. example pll configuration for the parallel interface parameter value output f vco 588 mhz (max) vt_sys_clk_div 1 vt_pix_clk_div 6 clk_pix 49 mpixel/s (= 588 mhz/12) clk_op 98 mpixel/s (= 588 mhz/6) output pixel rate 98 mpixel/s serial pll configuration figure 20. pll for the serial interface pre_pll_clk_div 2(1 ? 64) f vco extclk (6 ? 27 mhz) pll_multiplier 58(32 ? 384) vt_sys_clk_div 1(1, 2, 4, 6, 8, 10, 12, 14, 16) vt_pix_clk_div 6(4 ? 16) clk_pix 1/2 op_sys_clk_div constant ? 1 op_pix_clk_div 12(8, 10, 12) f vco clk_op f serial f serial_clk the sensor will use op_sys_clk_div and op_pix_clk_div to configure the output clock per lane (clk_op). the configuration will depend on the number of active lanes (1, 2, or 4) configured. to configure the sensor protocol and number of lanes, refer to ?serial configuration?.
ar0330cm www.onsemi.com 24 table 27. pll parameters for the serial interface symbol parameter min max unit extclk external clock 6 27 mhz f vco vco clock 384 768 mhz clk_pix readout clock ? 98 mpixel/s clk_op output clock ? 98 mpixel/s f serial output serial data rate per lane hispi mipi 300 384 700 768 mbps f serial_clk output serial clock speed per lane hispii mipi 150 192 350 384 mhz the serial output should be configured so that it adheres to the following rules: ? the maximum data-rate per lane (f serial ) is 768 mbps/lane (mipi) and 700 mbps/lane (hispi). ? the output pixel rate per lane (clk_op) should be configured so that the sensor output pixel rate matches the peak pixel rate (2 clk_pix): ? 4-lane: 4 clk_op = 2 clk_pix = pixel rate (max: 196 mpixel/s) ? 2-lane: 2 clk_op = 2 clk_pix = pixel rate (max: 98 mpixel/s) ? 1-lane: 1 clk_op = 2 clk_pix = pixel rate (max: 76 mpixel/s) table 28. example pll configurations for the serial interface parameter 4-lane 2-lane 1-lane unit 12-bit 10-bit 12-bit 10-bit 12-bit 10-bit 8-bit f vco 588 490 588 490 768 768 768 mhz vt_sys_clk_div 1 1 2 2 4 4 4 vt_pix_clk_div 6 5 6 5 6 5 4 op_sys_clk_div 1 1 1 1 1 1 1 op_pix_clk_div 12 10 12 10 12 10 8 f serial 588 490 588 490 768 768 768 mhz f serial_clk 294 245 294 245 384 384 384 mhz clk_pix 98 98 49 49 32 38.4 48 mpixel/s clk_op 49 49 49 49 64 76.8 96 mpixel/s pixel rate 196 196 98 98 64 76.8 96 mpixel/s
ar0330cm www.onsemi.com 25 pixel output interfaces parallel interface the parallel pixel data interface uses these output-only signals: ? fv ? lv ? pixclk ? d out [11:0] the parallel pixel data interface is disabled by default at power up and after reset. it can be enabled by programming r0x301a. table 30 shows the recommended settings. when the parallel pixel data interface is in use, the serial data output signals can be left unconnected. set reset_register[12] to disable the serializer while in parallel output mode. output enable control when the parallel pixel data interface is enabled, its signals can be switched asynchronously between the driven and high ? z under pin or register control, as shown in table 29. oe_bar pin is only available on the bare die version. table 29. output enable control oe_bar pin drive signals r0x301a ? b[6] description disabled 0 interface high ? z disabled 1 interface driven 1 0 interface high ? z x 1 interface driven 0 x interface driven configuration of the pixel data interface fields in r0x301a are used to configure the operation of the pixel data interface. the supported combinations are shown in table 30. table 30. configuration of the pixel data interface serializer disable r0x301a ? b[12] parallel enable r0x301a ? b[7] standby end-of-frame r0x301a ? b[7] description 0 0 1 power up default. serial pixel data interface and its clocks are enabled. transitions to soft standby are synchronized to the end of frames on the serial pixel data interface. 1 1 0 parallel pixel data interface, sensor core data output. serial pixel data interface and its clocks disabled to save power. transitions to soft standby are synchronized to the end of the current row readout on the parallel pixel data interface. 1 1 1 parallel pixel data interface, sensor core data output. serial pixel data interface and its clocks disabled to save power. transitions to soft standby are synchronized to the end of frames in the parallel pixel data interface. high speed serial pixel data interface the high speed serial pixel (hispi) interface uses four data and one clock low voltage differential signaling (lvds) outputs. ? slvsc_p ? slvsc_n ? slvs0_p ? slvs0_n ? slvs1_p ? slvs1_n ? slvs2_p ? slvs2_n ? slvs3_p ? slvs3_n the hispi interface supports three protocols, streaming s, streaming sp, and packetized sp. the streaming protocols conform to a standard video application where each line of active or intra-frame blanking provided by the sensor is transmitted at the same length. the packetized sp protocol will transmit only the active data ignoring line-to-line and frame-to-frame blanking data. these protocols are further described in the high-speed serial pixel (hispi) interface protocol specification v1.00.00. the hispi interface building block is a unidirectional differential serial interface with four data and one double data rate (ddr) clock lanes. one clock for every four serial data lanes is provided for phase alignment across multiple lanes. figure 21 shows the configuration between the hispi transmitter and the receiver.
ar0330cm www.onsemi.com 26 figure 21. hispi transmitter and receiver interface block diagram a camera containing the hispi transmitter a host (dsp) containing the hispi receiver tx phy0 rx phy0 dp0 dp0 dn0 dn0 dp1 dp1 dn1 dn1 dp2 dp2 dn2 dn2 dp3 dp3 dn3 dn3 cp0 cp0 cn0 cn0 hispi physical layer the hispi physical layer is partitioned into blocks of four data lanes and an associated clock lane. any reference to the phy in the remainder of this document is referring to this minimum building block. the phy will serialize a 10-, 12-, 14- or 16-bit data word and transmit each bit of data centered on a rising edge of the clock, the second on the falling edge of clock. figure 22 shows bit transmission. in this example, the word is transmitted in order of msb to lsb. the receiver latches data at the rising and falling edge of the clock. figure 22. timing diagram . . txpost txpre 1 ui lsb msb dn dp cn cp dll timing adjustment the specification includes a dll to compensate for differences in group delay for each data lane. the dll is connected to the clock lane and each data lane, which acts as a control master for the output delay buffers. once the dll has gained phase lock, each lane can be delayed in 1/8 unit interval (ui) steps. this additional delay allows the user to increase the setup or hold time at the receiver circuits and can be used to compensate for skew introduced in pcb design. if the dll timing adjustment is not required, the data and clock lane delay settings should be set to a default code of 0x000 to reduce jitter, skew, and power dissipation.
ar0330cm www.onsemi.com 27 figure 23. block diagram of dll timing adjustment delay del0[2:0] delay del1[2:0] delay delay del3[2:0] delay del2[2:0] delclock[2:0] data_lane0 data_lane1 data_lane2 data_lane3 clock_lane0 figure 24. delaying the clock_lane with respect to the data_lane datan (deln = 000) cp (delclock = 000) cp (delclock = 001) cp (delclock = 010) cp (delclock = 011) cp (delclock = 100) cp (delclock = 101) cp (delclock = 110) cp (delclock =111) increasing delclock_[2:0] increases clock delay 1 ui figure 25. delaying the data_lane with respect to the clock_lane datan (deln = 000) cp (delclock = 000) 1 ui increasing deln_[2:0] increases data delay datan (deln = 001) datan (deln = 010) datan (deln = 011) datan (deln = 100) datan (deln = 101) datan (deln = 110) datan (deln = 111) t dllstep
ar0330cm www.onsemi.com 28 hispi streaming mode protocol layer the hispi protocol is described hispi protocol v1.00.00 a. mipi interface the serial pixel data interface uses the following output-only signal pairs: ? data1_p ? data1_n ? data2_p ? data2_n ? data3_p ? data3_n ? data4_p ? data4_n ? clk_p ? clk_n the signal pairs use both single-ended and differential signaling, in accordance with the the mipi alliance specification for d ? phy v1.00.00. the serial pixel data interface is enabled by default at power up and after reset. the data0_p, data0_n, data1_p, data1_n, clk_p and clk_n pads are set to the ultra low power state (ulps) if the serial disable bit is asserted (r0x301a ? b[12] = 1) or when the sensor is in the hardware standby or soft standby system states. when the serial pixel data interface is used, the line_valid, frame_valid, pixclk and d out [11:0] signals (if present) can be left unconnected. serial configuration the serial format should be configured using r0x31ac. this register should be programmed to 0x0c0c when using the parallel interface. the r0x0112 ? 3 register can be programmed to any of the following data format settings that are supported: ? 0x0c0c ? sensor supports raw12 uncompressed data format ? 0x0c0a ? the sensor supports raw12 compressed format (10-bit words) using 12 ? 10 bit a ? law compression. see ?compression? section ? 0x0a0a ? sensor supports raw10 uncompressed data format. this mode is supported by discarding all but the upper 10 bits of a pixel value ? 0x0808 ? sensor supports raw8 uncompressed data format. this mode is supported by discarding all but the upper 8 bits of a pixel value (mipi only). the serial_format register (r0x31ae) register controls which serial interface is in use when the serial interface is enabled (reset_register[12] = 0). the following serial formats are supported: ? 0x0201 ? sensor supports single-lane mipi operation ? 0x0202 ? sensor supports dual-lane mipi operation ? 0x0204 ? sensor supports quad-lane mipi operation ? 0x0304 ? sensor supports quad-lane hispi operation the mipi timing registers must be configured differently for 10-bit or 12-bit modes. these modes should be configured when the sensor streaming is disabled. see table 31. table 31. recommended mipi timing configuration register configuration description 10-bit, 490 mbps/lane 12-bit, 588 mbps/lane clocking: continuous 0x31b0 40 36 frame preamble 0x31b2 14 12 line preamble 0x31b4 0x2743 0x2643 mipi timing 0 0x31b6 0x114e 0x114e mipi timing 1 0x31b8 0x2049 0x2048 mipi timing 2 0x31ba 0x0186 0x0186 mipi timing 3 0x31bc 0x8005 0x8005 mipi timing 4 0x31be 0x2003 0x2003 mipi config status
ar0330cm www.onsemi.com 29 pixel sensitivity figure 26. integration control in ers readout row reset (start of integration) row readout row integration (t integration ) a pixel?s integration time is defined by the number of clock periods between a row?s reset and read operation. both the read followed by the reset operations occur within a row period (t row ) where the read and reset may be applied to different rows. the read and reset operations will be applied to the rows of the pixel array in a consecutive order. the integration time in an ers frame is defined as: t integration t coarse t fine (eq. 13) the coarse integration time is defined by the number of row periods (t row ) between a row?s reset and the row read. the row period is the defined as the time between row read operations (see sensor frame rate section). t coarse t row coarse_integration_time (eq. 14) figure 27. example of 8.33 ms integration in 16.6 ms frame vertical blanking vertical blanking horizontal blanking reset read t coarse = coarse_integration_time t row 8.33 ms = 654 rows 12.7 s/row t frame = frame_length_lines t row 16.6 ms = 1308 rows 12.7 s/row image time the fine integration is then defined by the number of pixel clock periods between the row reset and row read operation within t row . this period is defined by the fine_integration_time register. figure 28. row read and row reset showing fine integration start of read row n and reset row k start of read row n+1 and reset row k+1 read row n reset row k t row = line_length_pck (1 / clk_pix) t fine = fine_integration_time (1 / clk_pix) t fine fine_integration_time clk_pix (eq. 15) the maximum allowed value for fine_integration_time is line_length_pck ? 1204. on semiconductor recommends that the fine_integration_time in the ar0330 be left at zero.
ar0330cm www.onsemi.com 30 figure 29. the row integration time is greater than the frame readout time vertical blanking vertical blanking horizontal blanking shutter pointer read pointer t coarse = coarse_integration_time t row 20.7 ms = 1634 rows 12.7 s/row t frame = frame_length_lines t row 16.6 ms = 1308 rows 12.7 s/row image horizontal blanking image extended vertical blanking time 4.1 ms the minimum frame-time is defined by the number of row periods per frame and the row period. the sensor frame-time will increase if the coarse_integration_time is set to a value equal to or greater than the frame_length_lines . the maximum integration time can be limited to the frame time by setting r0x30ce[5] to 1.
ar0330cm www.onsemi.com 31 gain stages the analog gain stages of the ar0330 sensor are shown in figure 30. the sensor analog gain stage consists of column amplifiers and a variable adc reference. the sensor will apply the same analog gain to each color channel. digital gain can be configured to separate levels for each color channel. figure 30. gain stages in ar0330 sensor adc reference digital gain with dithering 1x to 15.992x (128 steps per 6 db) ?xxxx.yyyy? xxxx(15 ? 0) yyyyyyy(127/128 to 0) coarse gain: 1x, 2x, 4x, 8x fine gain: 1 ? 2x: 16 steps 2 ? 4x: 8 steps 4 ? 8x: 4 steps the level of analog gain applied is controlled by the coarse_gain and fine_gain registers. the analog readout can be configured differently for each gain level. the recommended gain tables are listed in table 32. it is recommended that these registers are configured before streaming images. table 32. recommended sensor analog gain tables coarse_gain fine_gain total gain coarse_gain fine_gain total gain r0x3060[5:4] gain (x) r0x3060[3:0] gain (x) (x) (db) r0x3060[5:4] gain (x) r0x3060[3:0] gain (x) (x) (db) 0 1 0 1.00 1.00 0.00 0 1x 15 1.88 1.88 5.49 0 1 1 1.03 1.03 0.26 1 2x 0 1.00 2.00 6.00 0 1 2 1.07 1.07 0.56 1 2x 2 1.07 2.13 6.58 0 1 3 1.10 1.10 0.86 1 2x 4 1.14 2.29 7.18 0 1 4 1.14 1.14 1.16 1 2x 6 1.23 2.46 7.82 0 1 5 1.19 1.19 1.46 1 2x 8 1.33 2.67 8.52 0 1 6 1.23 1.23 1.80 1 2x 10 1.45 2.91 9.28 0 1 7 1.28 1.28 2.14 1 2x 12 1.60 3.20 10.10 0 1 8 1.33 1.33 2.50 1 2x 14 1.78 3.56 11.02 0 1 9 1.39 1.39 2.87 2 4x 0 1.00 4.00 12.00 0 1 10 1.45 1.45 3.25 2 4x 4 1.14 4.57 13.20 0 1 11 1.52 1.52 3.66 2 4x 8 1.33 5.33 14.54 0 1 12 1.60 1.60 4.08 2 4x 12 1.60 6.40 16.12 0 1 13 1.68 1.68 4.53 3 8x 0 1.00 8.00 18.00 0 1 14 1.78 1.78 5.00 each digital gain can be configured from a gain of 0 to 15.875. the digital gain supports 128 gain steps per 6 db of gain. the format of each digital gain register is ?xxxx.yyyyyyy? where ?xxxx? refers an integer gain of 1 to 15 and ?yyyyyyy? is a fractional gain ranging from 0/128 to 127/128. the sensor includes a digital dithering feature to reduce quantization resulting from using digital gain can be implemented by setting r0x30ba[5] to 1. the default value is 0. refer to ?real-time context switching? for the analog and digital gain registers in both context a and context b modes.
ar0330cm www.onsemi.com 32 data pedestal the data pedestal is a constant offset that is added to pixel values at the end of datapath. the default offset is 168 and is a 12-bit offset. this offset matches the maximum range used by the corrections in the digital readout path. the data pedestal value can be changed if the lock register bit (r0x301a[3]) is set to ?0?. this bit is set to ?1? by default. sensor readout image acquisition modes the ar0330 supports two image acquisition modes: ? electronic rolling shutter (ers) mode: this is the normal mode of operation. when the ar0330 is streaming; it generates frames at a fixed rate, and each frame is integrated (exposed) using the ers. when the ers is in use, timing and control logic within the sensor sequences through the rows of the array, resetting and then reading each row in turn. in the time interval between resetting a row and subsequently reading that row, the pixels in the row integrate incident light. the integration (exposure) time is controlled by varying the time between row reset and row readout. for each row in a frame, the time between row reset and row readout is the same, leading to a uniform integration time across the frame. when the integration time is changed (by using the two-wire serial interface to change register settings), the timing and control logic controls the transition from old to new integration time in such a way that the stream of output frames from the ar0330 switches cleanly from the old integration time to the new while only generating frames with uniform integration. see ?changes to integration time? in the ar0330 register reference. ? global reset mode: this mode can be used to acquire a single image at the current resolution. in this mode, the end point of the pixel integration time is controlled by an external electromechanical shutter, and the ar0330 provides control signals to interface to that shutter. the benefit of using an external electromechanical shutter is that it eliminates the visual artifacts associated with ers operation. visual artifacts arise in ers operation, particularly at low frame rates, because an ers image effectively integrates each row of the pixel array at a different point in time. window control the sequencing of the pixel array is controlled by the x_addr_start, y_addr_start, x_addr_end, and y_addr_end registers. the x_addr_start equal to 6 is the minimum setting value. the y_addr_start equal to 6 is the minimum setting value. please refer to table 33 and table 34 for details. table 33. pixel column configuration column address number type notes 0?5 6 active border columns 6?2309 2304 active active columns 2310?2315 6 active border columns table 34. pixel row configuration row address number type notes 2?5 4 active not used in case of ?edge effects? 6?1549 1544 active active rows 1550?1555 6 active not used in case of ?edge effects? readout modes horizontal mirror when the horizontal_mirror bit (r0x3040[14]) is set in the image_orientation register, the order of pixel readout within a row is reversed, so that readout starts from x_addr_end + 1and ends at x_addr_start. figure 31 shows a sequence of 6 pixels being read out with r0x3040[14] = 0 and r0x3040[14] = 1. changing r0x3040[14] causes the bayer order of the output image to change; the new bayer order is reflected in the value of the pixel_order register.
ar0330cm www.onsemi.com 33 figure 31. effect of horizontal mirror on readout order g0[11:0] g3[11:0] r0[11:0] r2[11:0] g1[11:0] g2[11:0] r1[11:0] r1[11:0] g2[11:0] g1[11:0] r2[11:0] r0[11:0] line_valid horizontal_mirror = 0 d out [11:0] horizontal_mirror = 1 d out [11:0] vertical flip when the vertical_flip bit (r0x3040[15]) is set in the image_orientation register, the order in which pixel rows are read out is reversed, so that row readout starts from y_addr_end and ends at y_addr_start. figure 32 shows a sequence of 6 rows being read out with r0x3040[15] = 0 and r0x3040[15] = 1. changing this bit causes the bayer order of the output image to change; the new bayer order is reflected in the value of the pixel_order register. figure 32. effect of vertical flip on readout order row0[11:0] row6[11:0] frame_valid vertical_flip = 0 d out [11:0] vertical_flip = 1 d out [11:0] row1[11:0] row5[11:0] row2[11:0] row4[11:0] row3[11:0] row3[11:0] row4[11:0] row2[11:0] row5[11:0] row1[11:0]
ar0330cm www.onsemi.com 34 subsampling the ar0330 supports subsampling. subsampling allows the sensor to read out a smaller set of active pixels by either skipping or binning pixels within the readout window. the working modes described in the data sheet that use subsampling are configured to use either 2x2 or 3x3 subsampling. figure 33. horizontal binning in the ar0330 sensor isb isb isb isb isb isb horizontal binning is achieved either in the pixel readout or the digital readout. the sensor will sample the combined 2x or 3x adjacent pixels within the same color plane. figure 34. vertical row binning in the ar0330 sensor e ? e ? e ? e ? vertical row binning is applied in the pixel readout. row binning can be configured of 2x or 3x rows within the same color plane. on semiconductor recommends not to use 3x binning in ar0330 as it may introduce some image artifacts. pixel skipping can be configured up to 2x and 3x in both the x-direction and y-direction. skipping pixels in the x-direction will not reduce the row time. skipping pixels in the y-direction will reduce the number of rows from the sensor effectively reducing the frame time. skipping will introduce image artifacts from aliasing. the sensor increments its x and y address based on the x_odd_inc and y_odd_inc value. the value indicates the addresses that are skipped after each pair of pixels or rows has been read. the sensor will increment x and y addresses in multiples of 2. this indicates that a greenr and red pixel pair will be read together. as well, that the sensor will read a gr-r row first followed by a b-gb row. x subsampling factor 1 x_odd_inc 2 (eq. 16) y subsampling factor 1 y_odd_inc 2 (eq. 17) a value of 1 is used for x_odd_inc and y_odd_inc when no pixel subsampling is indicated. in this case, the sensor is incrementing x and y addresses by 1 + 1 so that it reads consecutive pixel and row pairs. to implement a 2x skip in the x direction, the x_odd_inc is set to 3 so that the x address increment is 1 + 3, meaning that sensor will skip every other gr-r pair.
ar0330cm www.onsemi.com 35 table 35. configuration for horizontal subsampling x_odd_inc restrictions no subsampling x_odd_inc = 1 skip = (1+1) * 0.5 = 1x the horizontal fov must be programmed to meet the following rule: x_addr_end x_addr_start 1 x_odd_inc 2 even number skip 2x x_odd_inc = 3 skip = (1+3) * 0.5 = 2x skip 3x x_odd_inc = 5 skip = (1+5) * 0.5 = 3x analog bin 2x x_odd_inc = 3 skip = (1+3) * 0.5 = 2x col_sf_bin_en = 1 analog bin 3x x_odd_inc = 5 skip = (1+5) * 0.5 = 3x col_sf_bin_en = 1 digital bin 2x x_odd_inc = 3 skip = (1+3) * 0.5 =2x col_bin =1 digital bin 3x x_odd_inc = 5 skip = (1+5) * 0.5 = 3x col_bin = 1 table 36. configuration for vertical subsampling y_odd_inc restrictions no subsampling y_odd_inc = 1 skip = (1+1) * 0.5 = 1x row_bin = 0 the horizontal fov must be programmed to meet the following rule: y_addr_end y_addr_start 1 y_odd_inc 2 even number skip 2x y_odd_inc = 3 skip = (1+3) * 0.5 = 2x row_bin = 0 skip 3x y_odd_inc = 5 skip = (1+5) * 0.5 = 3x row_bin = 0 analog bin 2x y_odd_inc = 3 skip = (1+3) * 0.5 = 2x row_bin = 1 analog bin 3x y_odd_inc = 5 skip = (1+5) * 0.5 = 3x row_bin = 1
ar0330cm www.onsemi.com 36 sensor frame rate the time required to read out an image frame (t frame ) can be derived from the number of clocks required to output each image and the pixel clock. the frame-rate is the inverse of the frame period. fps 1 t frame (eq. 18) the number of clocks can be simplified further into the following parameters: ? the number of clocks required for each sensor row ( line_length_pck ) this parameter also determines the sensor row period when referenced to the sensor readout clock. (t row = line_length_pck 1/clk_pix) ? the number of row periods per frame ( frame_length_lines ) ? an extra delay between frames used to achieve a specific output frame period ( extra_delay ) t frame 1 clk_pix (eq. 19) (frame_length_lines line_length_pck extra_delay) figure 35. frame period measured in clocks vertical blanking (vb) active rows active columns horizontal blanking (hb) extra_delay line_length_pck = active columns + hb frame_length_lines = active rows + vb row period (t row ) the line_length_pck will determine the number of clock periods per row and the row period (t row ) when combined with the sensor readout clock. the line_length_pck includes both the active pixels and the horizontal blanking time per row. the sensor utilizes two readout paths, as seen in figure 18, allowing the sensor to output two pixels during each pixel clock. the minimum line_length_pck is defined as the maximum of the following three equations: adc readout limitation: 1024 (adc_high_speed) 0 (eq. 20) 1116 (adc_high_speed) 1(0) or options to modify this limit, as mentioned in the ?sequencer? section, can be found in the ar0330 developer guide. digital readout limitation: 1 3 x_addr_end x_addr_start (x_odd_inc 1) 0.5 (eq. 21) output interface limitations: 1 2 x_addr_end x_addr_start (x_odd_inc 1) 0.5 96 (eq. 22) row periods per frame the frame_length_lines determines the number of row periods (t row ) per frame. this includes both the active and blanking rows. the minimum_vertical_blanking value is defined by the number of ob rows read per frame, two embedded data rows, and two blank rows. minimum frame_length_lines y_addr_end y_addr_start y_odd_inc 1 2 (eq. 23) minimum _ vertical _ blanking the sensor is configured to output frame information in two embedded data rows by setting r0x3064[8] to 1 (default). if r0x3064[8] is set to 0, the sensor will instead output two blank rows. the data configured in the two embedded rows is defined in mipi csi ? 2 specification v1.00. table 37. minimum vertical blanking configuration r0x3180[0x00f0] ob rows minimum_vertical_blanking 0x8 (default) 8 ob rows 8 ob + 4 = 12 0x4 4 ob rows 4 ob + 4 = 8 0x2 2 ob rows 2 ob + 4 = 6 the locations of the ob rows, embedded rows, and blank rows within the frame readout are identified in figure 36.
ar0330cm www.onsemi.com 37 slave mode the slave mode feature of the ar0330 supports triggering the start of a frame readout from a vd signal that is supplied from an external asic. the slave mode signal allows for precise control of frame rate and register change updates. the vd signal is input to the trigger pin. both the gpi_en (r0x301a[8]) and the slave_mode (r0x30ce[4]) bits must be set to ?1? to enable the slave mode. figure 36. slave mode active state and vertical blanking start of frame n end of frame n start of frame n + 1 time frame valid ob rows (2, 4, or 8 rows) embedded data row (2 rows) active data rows blank rows (2 rows) extra vertical blanking (frame_length_lines ? min_frame_length_lines) vd signal slave mode active state extra delay (clocks) the period between the rising edge of the vd signal and the slave mode ready state is t frame = 16 clocks. if the slave mode is disabled, the new frame will begin after the extra delay period is finished. the slave mode will react to the rising edge of the input vd signal if it is in an active state. when the vd signal is received, the sensor will begin the frame readout and the slave mode will remain inactive for the period of one frame time minus 16 clock periods (t frame ? (16 / clk_pix)). after this period, the slave mode will re-enter the active state and will respond to the vd signal.
ar0330cm www.onsemi.com 38 figure 37. slave mode example with equal integration and frame readout periods (the integration of the last row is therefore started before the end of the programmed integration for the first row) inactive active row 0 row n inactive active rising edge rising edge row readout programmed integration slave mode trigger rising edge of vd signal triggers the start of the frame readout. row reset (start of integration) frame valid vd signal rising edge the slave mode will become ?active? after the last row period. both the row reset and row read operations will wait until the rising edge of the vd signal. row reset and read operations begin after the rising edge of the vd signal. integration due to slave mode delay the row shutter and read operations will stop when the slave mode becomes active and is waiting for the vd signal. the following should be considered when configuring the sensor to use the slave mode: 1. the frame period (t frame ) should be configured to be less than the period of the input vd signal. the sensor will disregard the input vd signal if it appears before the frame readout is finished. 2. if the sensor integration time is configured to be less than the frame period, then the sensor will not have reset all of the sensor rows before it begins waiting for the input vd signal. this error can be minimized by configuring the frame period to be as close as possible to the desired frame rate (period between vd signals). figure 38. slave mode example where the integration period is half of the frame readout period (the sensor read pointer will have paused at row 0 while the shutter pointer pauses at row n/2. the extra integration caused by the slave mode delay will only be seen by rows 0 to n/2. the example below is for a frame readout period of 16.6ms while the integration time is configured to 8.33 ms) inactive active row0 row n inactive active rising edge rising edge slave mode trigger frame valid vd signal rising edge reset operation is held during slave mode ?active? state. row reset and read operations begin after the rising edge of the vd signal. 8.33 ms 8.33 ms row readout programmed integration row reset (start of integration) integration due to slave mode delay
ar0330cm www.onsemi.com 39 when the slave mode becomes active, the sensor will pause both row read and row reset operations. note: the row integration period is defined as the period from row reset to row read. when the ar0330 is working in slave mode, the external trigger signal vd must have accurately controlled timing to avoid uneven exposure in the output image. the vd timing control should make the slave mode ?wait period? less than 32 pixel clocks. to avoid uneven exposure, programmed integration time cannot be larger than vd period. to increase integration time more than current vd period, the ar0330 must be configured to work at a lower frame rate and read out image with new vd to match the new timing. the period between slave mode pulses must also be greater than the frame period. if the rising edge of the vd pulse arrives while the slave mode is inactive, the vd pulse will be ignored and will wait until the next vd pulse has arrived.
ar0330cm www.onsemi.com 40 frame readout the sensor readout begins with vertical blanking rows followed by the active rows. the frame readout period can be defined by the number of row periods within a frame ( frame_length_lines ) and the row period ( line_length_pck ). the sensor will read the first vertical blanking row at the beginning of the fram e period and the last active row at the end of the row period. figure 39. example of the sensor output of a 2304 1296 frame at 60 fps (the frame valid and line valid signals mentioned in this diagram represent internal signals within the sensor. the sync codes represented in this diagram represent the hispi streaming sp protocol) active rows vertical blanking time 1/60s end of frame readout end of frame readout start of vertical blanking start of frame start of active row end of line serial sync codes end of frame row reset row read row reset row read frame valid line valid 1/60s row reset row read row reset row read 2304 x 1296 2304 x 1296 hb (192 pixels/column) hb (192 pixels/column) vb (12 rows) vb (12 rows) frame 39 aligns the frame integration and readout operation to the sensor output. it also shows the sensor output using the hispi streaming sp protocol. different sensor protocols will list different sync codes. table 38. serial sync codes included with each protocol included with the ar0330 sensor interface/protocol start of vertical blanking row (sov) start of frame (sof) start of active line (soa) end of line (eol) end of frame (eof) parallel parallel interface uses frame valid (fv) and line valid (lv) outputs to denote start and end of line and frame. hispi streaming s yes send sov yes no sync code no sync code hispi streaming sp yes yes yes yes yes hispi packetized sp no sync code yes yes yes yes mipi no sync code yes yes yes yes figure 40 illustrates how the sensor active readout time can be minimized while reducing the frame rate. 1308 vb rows were added to the output frame to reduce the 2304 1296 frame rate from 60 fps to 30 fps without increasing the delay between the readout of the first and last active row.
ar0330cm www.onsemi.com 41 figure 40. example of the sensor output of a 2304 1296 frame at 30 fps (the frame valid and line valid signals mentioned in this diagram represent internal signals within the sensor. the sync codes represented in this diagram represent the hispi streaming sp protocol) hb (192 pixels) hb (192 pixels) frame valid line valid 1/30s active rows vertical blanking end of frame readout row reset row read row reset 2304 x 1296 2304 x 1296 row reset row read row reset row read end of frame readout time start of vertical blanking start of frame start of active row end of line serial sync codes end of frame 1/30s row read vb (1320 rows) vb (1320 rows)
ar0330cm www.onsemi.com 42 changing sensor modes register changes all register writes are delayed by 1x frame. a register that is written to during the readout of frame n will not be updated to the new value until the readout of frame n+2 . this includes writes to the sensor gain and integration registers. real-time context switching in the ar0330, the user may switch between two full register sets a and b by writing to a context switch change bit in r0x30b0[13]. when the context switch is configured to context a the sensor will reference the ?context a registers?. if the context switch is changed from a to b during the readout of frame n , the sensor will then reference the context b coarse_integration_time registers in frame n+1 and all other context b registers at the beginning of reading frame n+2 . the sensor will show the same behavior when changing from context b to context a. table 39. list of configurable registers for context a and context b context a context b register description address register description address coarse_integration_time 0x3012 coarse_integration_time_cb 0x3016 fine_integration_time 0x3014 fine_integration_time_cb 0x3018 line_length_pck 0x300c line_length_pck_cb 0x303e frame_length_lines 0x300a frame_length_lines_cb 0x30aa col_sf_bin_en 0x3040[9] col_sf_bin_en_cb 0x3040[8] row_bin 0x3040[12] row_bin_cb 0x3040[10] col_bin 0x3040[13] col_bin_cb 0x3040[11] fine_gain 0x3060[3:0] fine_gain_cb 0x3060[11:8] coarse_gain 0x3060[5:4] coarse_gain_cb 0x3060[13:12] x_addr_start 0x3004 x_addr_start_cb 0x308a y_addr_start 0x3002 y_addr_start_cb 0x308c x_addr_end 0x3008 x_addr_end_cb 0x308e y_addr_end 0x3006 y_addr_end_cb 0x3090 y_odd_inc 0x30a6 y_odd_inc_cb 0x30a8 x_odd_inc 0x30a2 x_odd_inc_cb 0x30ae adc_high_speed 0x30ba[6] adc_high_speed_cb 0x30ba[7] green1_gain 0x3056 green1_gain_cb 0x30bc blue_gain 0x3058 blue_gain_cb 0x30be red_gain 0x305a red_gain_cb 0x30c0 green2_gain 0x305c green2_gain_cb 0x30c2 global_gain 0x305e global_gain_cb 0x30c4 note: on semiconductor recommends leaving fine_integration_time at 0.
ar0330cm www.onsemi.com 43 figure 41. example of changing the sensor from context a to context b active rows vertical blanking 1/60s 1/60s end of frame readout end of frame readout end of frame readout 1/54s frame n vb (12 rows) hb (192 pixels/column) vb (12 rows) hb (192 pixels/column) vb (12 rows) hb (192 pixels/column) write context a to b during readout of frame n integration time of context b mode implemented during readout of frame n+1 context b mode is implemented in frame n+2 2304 x 1296 frame n+1 2048 x 1536 frame n+2 2304 x 1296 time start of vertical blanking end of line serial sync codes end of frame start of frame start of active row
ar0330cm www.onsemi.com 44 compression the sensor can optionally compress 12-bit data to 10-bit using a-law compression. the compression is applied after the data pedestal has been added to the data. see figure 1. the a-law compression is disabled by default and can be enabled by setting r0x31d0 from ?0? to ?1?. table 40. a-law compression table for 12 ? 10 bits input range input values compressed codeword 11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 0 to 127 0 0 0 0 0 a b c d e f g 0 0 0 a b c d e f g 128 to 255 0 0 0 0 1 a b c d e f g 0 0 1 a b c d e f g 256 to 511 0 0 0 1 a b c d e f g x 0 1 0 a b c d e f g 512 to 1023 0 0 1 a b c d e f g x x 0 1 1 a b c d e f g 1024 to 2047 0 1 a b c d e f g h x x 1 0 a b c d e f g h 2048 to 4095 1 a b c d e f g h x x x 1 1 a b c d e f g h test patterns the ar0330 has the capability of injecting a number of test patterns into the top of the datapath to debug the digital logic. with one of the test patterns activated, any of the datapath functions can be enabled to exercise it in a deterministic fashion. test patterns are selected by test_pattern_mode register (r0x3070). only one of the test patterns can be enabled at a given point in time by setting the test_pattern_mode register according to table 41. when test patterns are enabled the active area will receive the value specified by the selected test pattern and the dark pixels will receive the value in test_pattern_green (r0x3074 and r0x3078) for green pixels, test_pattern_blue (r0x3076) for blue pixels, and test_pattern_red (r0x3072) for red pixels. table 41. test pattern modes test_pattern_mode test pattern output 0 no test pattern (normal operation) 1 solid color 2 100% vertical color bars 3 fade-to-gray vertical color bars 256 walking 1s test pattern (12-bit) solid color when the color field mode is selected, the value for each pixel is determined by its color. green pixels will receive the value in test_pattern_green, red pixels will receive the value in test_pattern_red, and blue pixels will receive the value in test_pattern_blue. vertical color bars when the vertical color bars mode is selected, a typical color bar pattern will be sent through the digital pipeline. walking 1s when the walking 1s mode is selected, a walking 1s pattern will be sent through the digital pipeline. the first value in each row is 1.
ar0330cm www.onsemi.com 45 two-wire serial register interface the two-wire serial interface bus enables read/write access to control and status registers within the ar0330. this interface is designed to be compatible with the electrical characteristics and transfer protocols of the i 2 c specification. the interface protocol uses a master/slave model in which a master controls one or more slave devices. the sensor acts as a slave device. the master generates a clock (s clk ) that is an input to the sensor and is used to synchronize transfers. data is transferred between the master and the slave on a bidirectional signal (s data ). s data is pulled up to v dd _ io off-chip by a 1.5 k resistor. either the slave or master device can drive s data low ? the interface protocol determines which device is allowed to drive s data at any given time. the protocols described in the two-wire serial interface specification allow the slave device to drive s clk low; the ar0330 uses s clk as an input only and therefore never drives it low. protocol data transfers on the two-wire serial interface bus are performed by a sequence of low-level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no-) acknowledge bit 4. a message byte 5. a stop condition the bus is idle when both s clk and s data are high. control of the bus is initiated with a start condition, and the bus is released with a stop condition. only the master can generate the start and stop conditions. start condition a start condition is defined as a high-to-low transition on s data while s clk is high. at the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a ?repeated start? or ?restart? condition. stop condition a stop condition is def ined as a low -to-high transition on s data while s clk is high. data transfer data is transferred serially, 8 bits at a time, with the msb transmitted first. each byte of data is followed by an acknowledge bit or a no-acknowledge bit. this data transfer mechanism is used for both the slave address/data direction byte and for message bytes. one data bit is transferred during each s clk clock period. s data can change when s clk is low and must be stable while s clk is high. slave address/data direction byte bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. a ?0? in bit [0] indicates a write, and a ?1? indicates a read. the default slave addresses used by the ar0330 sensor are 0x20 (write address) and 0x21 (read address). alternate slave addresses of 0x30 (write address) and 0x31 (read address) can be selected by asserting the s addr signal (tie high). alternate slave addresses can also be programmed through r0x31fc. message byte message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. acknowledge bit each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the s clk clock period following the data transfer. the transmitter (which is the master when writing, or the slave when reading) releases s data . the receiver indicates an acknowledge bit by driving s data low. as for data transfers, s data can change when s clk is low and must be stable while s clk is high. no-acknowledge bit the no-acknowledge bit is generated when the receiver does not drive s data low during the s clk clock period following a data transfer. a no-acknowledge bit is used to terminate a read sequence. typical sequence a typical read or write sequence begins by the master generating a start condition on the bus. after the start condition, the master sends the 8-bit slave address/data direction byte. the last bit indicates whether the request is for a read or a write, where a ?0? indicates a write and a ?1? indicates a read. if the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. if the request was a write, the master then transfers the 16-bit register address to which the write should take place. this transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. the master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence. the master stops writing by generating a (re)start or stop condition. if the request was a read, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same way as with a write request. the master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, eight bits at a time. the master generates an acknowledge bit after each 8-bit transfer. the slave?s internal register address is automatically incremented after every 8 bits are transferred. the data transfer is stopped when the master sends a no-acknowledge bit.
ar0330cm www.onsemi.com 46 single read from random location this sequence (figure 42) starts with a dummy write to the 16-bit address that is to be used for the read. the master terminates the write by generating a restart condition. the master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. the master terminates the read by generating a no-acknowledge bit followed by a stop condition. figure 42 shows how the internal register address maintained by the ar0330 is loaded and incremented as the sequence proceeds. figure 42. single read from random location previous reg address, n reg address, m m+1 s0 1 p a sr slave address reg address[15:8] reg address[7:0] slave address s = start condition p = stop condition sr = restart condition a = acknowledge a = no-acknowledge slave to master master to slave a a a a read data single read from current location this sequence (figure 43) performs a read using the current value of the ar0330 internal register address. the master terminates the read by generating a no-acknowledge bit followed by a stop condition. the figure shows two independent read sequences. figure 43. single read from current location previous reg address, n reg address, n+1 n+2 s1 p slave address aa read data s1 p slave address aa read data sequential read, start from random location this sequence (figure 44) starts in the same way as the single read from random location (figure 42). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 44. sequential read, start from random location previous reg address, n reg address, m s0 slave address a a reg address[15:8] p a m+1 a a a 1 sr reg address[7:0] read data slave address m+l m+l ? 1 m+l ? 2 m+1 m+2 m+3 a read data a read data a read data read data
ar0330cm www.onsemi.com 47 sequential read, start from current location this sequence (figure 45) starts in the same way as the single read from current location (figure 43). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 45. sequential read, start from current location n+l n+l ? 1 n+2 n+1 previous reg address, n p a s 1 read data a slave address read data read data read data aaa single write to random location this sequence (figure 46) begins with the master generating a start condition. the slave address/data direction byte signals a write and is followed by the high then low bytes of the register address that is to be written. the master follows this with the byte of write data. the write is terminated by the master generating a stop condition. figure 46. single write to random location previous reg address, n reg address, m m+1 s0 p slave address reg address[15:8] reg address[7:0] a a a a a write data sequential write, start at random location this sequence (figure 47) starts in the same way as the single write to random location (figure 46). instead of generating a stop condition after the first byte of data has been transferred, the master continues to perform byte writes until ?l? bytes have been written. the write is terminated by the master generating a stop condition. figure 47. sequential write, start at random location previous reg address, n reg address, m m+1 s0 slave address a reg address[15:8] a a a reg address[7:0] write data m+l m+l ? 1 m+l ? 2 m+1 m+2 m+3 write data a a a ap a write data write data write data
ar0330cm www.onsemi.com 48 spectral characteristics figure 48. bare die quantum efficiency wavelength (nm) 350 quantum efficiency (%) 0 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 1150 10 20 30 40 50 60 70 red green blue cra vs. image height plot image height cra (%) (mm) (deg) chief ray angle (degrees) image height (%) ar0330 cra characteristic 0 10 2030 40506070 8090100110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0 0 0 5 0.152 0.80 10 0.305 1.66 15 0.457 2.54 20 0.609 3.42 25 0.761 4.28 30 0.914 5.11 35 1.066 5.94 40 1.218 6.75 45 1.371 7.57 50 1.523 8.37 55 1.675 9.16 60 1.828 9.90 65 1.980 10.58 70 2.132 11.15 75 2.284 11.57 80 2.437 11.80 85 2.589 11.78 90 2.741 11.48 95 2.894 10.88 100 3.046 9.96 note: the cra listed in the advanced data sheet described the 2048 1536 field of view (2.908 mm image height). this information was sufficient for configuring the sensor to read both the 4:3 (2048 1536) and 16:9 (2304 1296) aspect ratios. the cra information listed in the data sheet has now been updated to represent the entire pixel array (2304 1536). figure 49. chief ray angle (cra) ? 12
ar0330cm www.onsemi.com 49 cra vs. image height plot image height cra (%) (mm) (deg) chief ray angle (degrees) image height (%) ar0330 cra characteristic 0 10 2030 40506070 8090100110 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 0 0 0 5 0.152 1.10 10 0.305 2.20 15 0.457 3.30 20 0.609 4.40 25 0.761 5.50 30 0.914 6.60 35 1.066 7.70 40 1.218 8.80 45 1.371 9.90 50 1.523 11.00 55 1.675 12.10 60 1.828 13.20 65 1.980 14.30 70 2.132 15.40 75 2.284 16.50 80 2.437 17.60 85 2.589 18.70 90 2.741 19.80 95 2.894 20.90 100 3.046 22.00 note: the cra listed in the advanced data sheet described the 2048 1536 field of view (2.908 mm image height). this information was sufficient for configuring the sensor to read both the 4:3 (2048 1536) and 16:9 (2304 1296) aspect ratios. the cra information listed in the data sheet has now been updated to represent the entire pixel array (2304 1536). figure 50. chief ray angle (cra) ? 21 cra vs. image height plot image height cra (%) (mm) (deg) chief ray angle (degrees) image height (%) ar0330 cra characteristic 0 10 2030 40506070 8090100110 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 0 0 0 5 0.152 2.24 10 0.305 4.50 15 0.457 6.75 20 0.609 8.95 25 0.761 11.11 30 0.914 13.19 35 1.066 15.20 40 1.218 17.10 45 1.371 18.88 50 1.523 20.50 55 1.675 21.95 60 1.828 23.18 65 1.980 24.17 70 2.132 24.89 75 2.284 25.35 80 2.437 25.54 85 2.589 25.51 90 2.741 25.33 95 2.894 25.11 100 3.046 25.01 note: the cra listed in the advanced data sheet described the 2048 1536 field of view (2.908 mm image height). this information was sufficient for configuring the sensor to read both the 4:3 (2048 1536) and 16:9 (2304 1296) aspect ratios. the cra information listed in the data sheet has now been updated to represent the entire pixel array (2304 1536). figure 51. chief ray angle (cra) ? 25
ar0330cm www.onsemi.com 50 read the sensor cra follow the steps below to obtain the cra value of the image sensor: 1. set the register bit field r0x301a[5] = 1. 2. read the register bit fields r0x31fa[11:9]. 3. determine the cra value according to table 42. table 42. cra value binary value of r0x31fa[11:9] cra value 000 0 001 21 010 25 011 12
ar0330cm www.onsemi.com 51 packages the ar0330 comes in two packages: ? clcc package ? csp hispi/mipi package package dimensions clcc48 case 848au issue o
ar0330cm www.onsemi.com 52 package dimensions e e package center=die center(0,0) top view (image side) bottom view (bga side) unit:um package size:6278.15*6648.15 ball diameter:250 ball pitch:650 a b c d e f g h 8 7 6 5 4 3 2 1 c4 c c3 c2 c1 cross ? section view (e ? e) notch a b optical center( ? 290,230) a b c d e f g h 8 7 65 4 3 21 package center=die center(0,0) optical center(290,230) first clear pixel( ? 1987.5,2776.5) last clear pixel(1407.5, ? 2316.5) s2 j2 j1 s1 odcsp64 case 570bh issue o table 43. csp (mipi/hispi) package dimensions parameter symbol nom min max nom min max millimeters inches package body dimension x a 6.278 6.253 6.303 0.247 0.246 0.248 package body dimension y b 6.648 6.623 6.673 0.262 0.261 0.263 package height c 0.700 0.645 0.745 0.028 0.025 0.029 cavity height (glass to pixel distance) c4 0.041 0.037 0.045 0.002 0.001 0.002 glass thickness c3 0.400 0.390 0.410 0.016 0.015 0.016 package body thickness c2 0.570 0.535 0.605 0.022 0.021 0.024 ball height c1 0.130 0.100 0.160 0.005 0.004 0.006 ball diameter d 0.250 0.220 0.280 0.010 0.009 0.011 total ball count n 64 ball count x axis n1 8 ball count y axis n2 8 ubm u 0.280 0.270 0.290 0.011 0.011 0.011 pins pitch x axis j1 0.650 0.026 pins pitch y axis j2 0.650 0.026 bga ball center to package center offset in x-direction x 0.000 ? 0.025 0.025 0.000 ? 0.001 0.001 bga ball center to package center offset in y-direction y 0.000 ? 0.025 0.025 0.000 ? 0.001 0.001 bga ball center to chip center offset in x-direction x1 0.000 ? 0.014 0.014 0.000 ? 0.001 0.001 bga ball center to chip center offset in y-direction y1 0.000 ? 0.014 0.014 0.000 ? 0.001 0.001 edge to ball center distance along x s1 0.864 0.834 0.894 0.034 0.033 0.035 edge to ball center distance along y s2 1.049 1.019 1.079 0.041 0.040 0.042
ar0330cm www.onsemi.com 53 package orientation in camera design in a camera design, the package should be placed in a pcb so that the first clear pixel is located at the bottom left of the package (look at the package). this orientation will ensure that the image captured using a lens will be oriented correctly. figure 52. image orientation with relation to camera lens lens the package is oriented so that the first clear pixel is located in bottom left. the package pin locations after the sensor has been oriented correctly can be shown below. figure 53. first clear pixel and pin location (looking down on cover glass) 1 ???????????? 8 (2304,1536) first clear (0,0) a ??????????????? h pixel array (0,0) (2304,1536) csp package clcc package 1 48 pin orientation pixel first clear pixel on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular pu rpose, nor does on semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without li mitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, regulatio ns and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semicond uctor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typicals? mus t be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the rights of others. on semiconduc tor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or si milar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, cost s, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer . this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ar0330cm/d a ? pix is a trademark trademarks of semiconductor components industries, llc (scillc) or its subsidiaries in the united states and /or other countries. all other brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders. literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ?

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